This invention relates generally to advanced flash IC (integrated circuit) chips which includes a state machine for performing built-in self-test functions. More particularly, the present invention relates to an improved built-in self-test frontend state machine and a method for micro-architectural implementation of the same which is achieved with a minimal amount of test logic circuitry.
As is generally well-known, flash IC chips have become widely used in almost all forms of electronic devices such as cell-phones, digital camera, computers, PDA and many others. As flash memory IC chips are being used more and more, there has been a growing trend of requiring increased demands from flash designers in many characteristics of the flash manufacturing processes, such as reliability.
For example, since these flash IC chips are quite complex in nature, flash chips manufacturers have to manually test these chips before they are being shipped to customers. This process of manual testing is tedious and requires much effort, not to mention the high cost involved. With this in mind, flash chips manufacturers have implemented a method of built-in self-test circuitry on the flash memory IC chip so as to perform internal hardware tests on the various types of integrated circuits associated with the flash chip before they are shipped to the customers. This built-in self-test would make all the necessary tests on its own with only a minimal external hardware and minimal manual supervision. This capability of having built-in self-test circuitry eliminates the need of expensive hardware testers which greatly increases the overall manufacturing cost.
It is already known that a conventional state machine could be used to implement the logic functionality of a built-in self-test (BIST) frontend state machine for performing a sequence of logic states so as to control the testing process. A flow chart illustrating the logic functionality required to be implemented for the BIST frontend state machine is shown in FIG. 1. Unfortunately, the use of the conventional state machine to perform this functionality would require a large amount of logic gates in view of the many different states as well as the many different logic gates required to be implemented for each of the decision blocks. Thus, the conventional state machine approach suffers from the disadvantages of being too large and requiring a relatively large amount of chip area or real estate on a silicon I.C. chip or die containing the state machine.
Therefore, it would be desirable to provide an improved built-in self-test frontend state machine which performs the same logic functionality of the BIST frontend sequencing of states while minimizing the number of electrical circuit components. This is accomplished in the present invention by the provision of a state controller for generating output state signals based upon a fixed number of states utilizing xe2x80x9cdeath logicxe2x80x9d state transition.
Accordingly, it is a general object of the present invention to provide an improved built-in self-test frontend state machine and a method for micro-architectural implementation of the same.
It is another object of the present invention to provide an improved built-in self-test frontend state machine which is achieved with a minimal amount of test logic circuitry.
It is another object of the present invention to provide an improved built-in self-test frontend state machine which minimizes the test logic circuitry required to implement the BIST functionality by utilizing a xe2x80x9cdeath logicxe2x80x9d state transition technique.
It is still another object of the present invention to provide an improved built-in self-test frontend state machine which includes a state controller for generating output state signals based upon a fixed number of states so as to sequence through a set of tests to be executed.
In a preferred embodiment of the present invention, there is provided an improved BIST frontend state machine which includes a shift register which is responsive to values inputted by a user for generating output register signals corresponding to which one of a plurality of sets of tests are to be executed. A clock module is provided for generating two-phase non-overlapping clock signals. A backend state machine is provided for generating control signals indicative of whether an individual test is still being executed, has been completed, or has failed.
A state controller is responsive to the clock signals, control signals, and output register signals for generating output state signals based upon a-fixed number of states utilizing death logic transitions so as to sequence through the one of the plurality of sets of tests until completed or failed. A logic module is used to generate output test signals required for each individual test of the set of the plurality of sets of tests being sequenced through in response to the output register signals and the output state signals.